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DSP Group Announces Evaluation Development Platform (EDP) Based Dual Mac Teak Core

San Jose, California, DSP World Spring, Design Conference, April 11, 2000 -DSP Group (NASDAQ: DSPG), a leader in the developing and licensing of high-performance, cost-effective digital signal processors cores, announced today the availability of the Teak® Evaluation Development Platform (EDP) providing design environment for Teak-based System-on-a-Chip (SoC). The platform includes the low-power, fully synthesizable, dual MAC Teak DSP core.

The Teak EDP incorporates the Teak development chip with a built-in run-time emulator, JTAG interface, 128K words on-chip program RAM, 32K words data RAM, interrupt controller, Bus Interface Unit, general purpose I/O ports, hardware acceleration interface and clock generator. The chip was manufactured by TSMC in 0.25u CMOS process.

The evaluation platform also contains dual 16-bit codecs, on-board flash for stand-alone operation with on-board programming options, parallel port interface, 2 banks of 256K words RAM with an option of four banks of 256K words, up to 60K words data memory and a user-defined prototyping area.

"The Teak EDP combines all the necessary hardware and software components for system providers to evaluate and develop a complete System-on-a-Chip based on the Teak core,” said Erez Bar-Niv, Director of R&D in DSP Group's Technology Licensing division. “With EDP our licensees can smoothly evaluate various application configurations and come out with the best cost/performance structure,” added Bar-Niv.

The Teak core is the third generation of licensable DSP cores in the company's portfolio of leading-edge DSP core technology solutions. It follows in the footsteps of the PineDSPCore®, the OakDSPCore® and the TeakLite™ DSP Core. The Teak constitutes the basis for the PalmDSPCore.

Immediate markets for Teak include the existing OakDSPCore and TeakLite customers seeking improved performance at affordable prices, as well as a fast-growing marketplace of potential new customers looking for high-volume, cost-effective DSP core solutions. Teak is aimed at high performance-oriented applications such as cellular 3G, xDSL, VoIP Gateways and digital still camera.

The Teak core is a Dual MAC DSP, with parallel instruction capability and can read or write double words from/to a memory. This doubles the performance in critical and commonly used algorithms such as FIR and complex multiplication and improves the C-/C++ compiler performance. Special emphasis was given to FFT, Viterbi Decoder and trace-back algorithms. Adding dedicated built-in hardware accelerators and special addressing modes results in FFT Butterfly execution in 5 cycles and Viterbi's two Add-Compare-Select routine in 3 cycles.

The Teak is the only Dual MAC architecture in the market using a 16-bit instruction word resulting in a complete parallel instruction. The Teak code density leads to a substantial savings in code size, which reduces die size, overall cost and power consumption.

Teak was designed to support control tasks. In addition, its program memory space is 256K linear and up to 4M word using the built-in paging mechanism. Thus, the Teak can efficiently handle very large programs which are needed when the DSP is used for both DSP and massive control functions. Dedicated mechanisms were also added to support real-time operating systems, such as unlimited nesting levels of zero-overhead mechanisms (Block-Repeat and Repeat) and wide Automatic Context Switching. The System Interface of the core incorporates a Vectored Interrupt, advanced DMA modes of operation (Burst Mode and Cycle Stealing) and user-definable data memory size.

The Teak's instruction-set is binary compatible with the TeakLite and the OakDSPCore, allowing the re-use of software investment. The programmer or the C/C++ compiler can speed up performance by the local replacement of instructions.

The licensable Teak was designed to be a fully-synthesizable core – otherwise referred to as a 'soft core' design, which can easily be converted or "ported" into different technologies and foundries using fully automated methods. As a result, time-to-market is significantly reduced. The core is single edge design and uses a JTAG interface for both debugging and emulation.

About DSP Group, Inc.

DSP Group, Inc. is a global leader in the development and marketing of high-performance, cost-effective, licensable digital signal processing cores. The company's family of DSP cores provide ideal solutions for low-power speech and audio processing, wireless communication technologies such as 3G, GSM and CDMA, broadband modems, multimedia, advanced telecommunication systems, disk drive controllers and many other types of embedded control applications. By combining its DSP core technologies with its proprietary, advanced speech-processing algorithms – DSP Group also delivers a wide range of enabling, application specific ICs for full-featured integrated telephony products and applications, including digital spread- spectrum wireless technologies. DSP Group, Inc. maintains an international presence with offices located around the globe.

This press release is also available through DSP Group's News on Call fax service, which can be reached at 800-758-5804, company code 112025.

PalmDSPCore®, TeakDSPCore®, Teak®, OakDSPCore® and PineDSPCore®, are registered trademarks of DSP Group, Inc. TeakLite™ and SmartCores™ are trademarks of DSP Group, Inc. All other trade names and registration marks are the property of their respective holders.

Bat-Sheva Ovadia
Director of Marketing and Business Development
Technology Licensing Division,
Tel: (972) 9-952-9616
e-mail: batsheva@dsp.co.il